This invention relates generally to metal-insulator-semiconductor (MIS) devices and production methods and more particularly to improving the ability 16 scale-down and manufacturing consistency in the performance characteristics of MIS semiconductor devices having lightly-doped diffusion (LDD) structures.
As microminiaturization of metal-oxide-semiconductor (MOS) transistors progresses to ever smaller geometries, two different effects are becoming larger and larger problems due to short-channel limitations. These are the "punch-through" and "hot-carrier injection" effects. For a bipolar transistor with a very narrow base width, or a base with relatively low doping, breakdown can be caused by the punch-through effect, in which the neutral base width is reduced to zero at a sufficient Vcb and the collector depletion region is in direct contact with the emitter depletion region. In a MOS transistor, a concentration of the electric field at the end of the drain causes hot carriers to be captured mainly at the interface between the substrate and the insulator film or in the insulator film. The operating characteristics of such MOS transistors can drift, due to an accumulation of the electric charge. As the size of MOSFET gates decreases with advancing technology, MOS transistors used in very-large-scale integration (VLSI) circuits have been constrained by the voltage on the drain concentrating in the vicinity of the gate. This intensification causes a deterioration in the performance of the semiconductor device due a naturally occurring infusion of hot-carriers.
The state of the art has advanced beyond using 1.2 micron to 1.3 micron processes. As a result, transistors with lightly doped drain (LDD) structures have become one of the most popular types used, because the hot-carrier problem is alleviated in such structures. FIGS. 1A-1D show cross sections of a typical prior art LDD transistor after each of the principal manufacturing steps in a prior art process. In FIG. 1A, an n-well 22 and p-well 23 have been diffused in n-type silicon substrate 21. A LOCOS oxide layer 24 is then formed with a selective oxide method. Around LOCOS oxide layer 24 an oxide film 25 is formed. A polycrystalline silicon film is deposited, followed by an n.sup.+ diffusion that produces an n.sup.+ polycrystalline silicon layer which is highly conductive. Selective etching of the n.sup.+ polycrystalline silicon layer results in gate electrode 26. A light oxidation step, using an oxygen atmosphere, forms oxide film 27. In FIG. 1B, p-type diffusions 28 are selectively implanted using boron ions. One diffusion 28 forms the source and the other diffusion 28 forms the drain of a p-channel transistor thus created. (The drain and source are practically interchangeable.) The implantation energy used runs from a low of 20 Kev to a high of 40 Kev. The p-type first implantation concentration is preferably within the range of 5.times.10.sup.12 /cm.sup.2 to 5.times.10.sup.13 /cm.sup.2. Another implantation step, this time n-type using phosphorous ions, produces diffusions 29 in p-well 23. These diffusions result in source and drain areas of an n-channel transistor. The implantation energy used typically ranges from 30 Key to 60 Kev, to produce the most desirable n-type first implantation concentration of impurity atoms between 5.times.10.sup.12 /cm.sup.2 and 5.times.10.sup.13 /cm.sup.2. An oxygen atmosphere and a CVD deposition method then are combined to deposit a silicon dioxide layer 30 that has a film thickness of between 2000 and 4000 angstroms (.ANG.). FIG. 1C shows that on each side of gate electrode 26, a sidewall 31 remains after anisotropic etching away of the other areas of layers 27 and 30. The gate 26 and sidewall 31 are then used to shadow (mask) the substrate under the two of them from receiving a heavy impurity concentration in the next few steps. A p-type second diffusion layer 32 drives into most of layer 28 deeper and with a heavier concentration of boron ions. The implantation energy in this p-type second diffusion preferably is set between 20 Key and 60 Kev. The most desirable implantation concentration at this point is a low of 1.times.10.sup.15 /cm.sup.2 to a high of 1.times.10.sup. 16 /cm.sup.2. A n-type second diffusion layer 33 is driven in to replace most of layer 29 by implanting arsenic ions. The implantation energy is preferably set between 40 Key and 80 Key. The implantation concentration should best be targeted to be between 1.times.10.sup.15 /cm.sup.2 and 1.times.10.sup.16 /cm.sup.2. FIG. 1D shows a CVD deposited silicon dioxide layer 34 covering gate electrodes 26. Then contact holes are etched to give access to diffusions 32 and 33. An aluminum interconnect layer 35 is then deposited which connects to the diffusions 32 and 33 through the accesses in layer 34.
It is difficult, however, to control the width of sidewalls 31 to have a uniform film thickness, or a target film thickness, over the entire surface of a 5-inch or 6-inch semiconductor wafer. A variety of processing methods are used in the prior art to form sidewalls 31, including low-pressure, plasma formation, and atmospheric pressure methods. Any of these methods typically has a.+-.20% variation in target film thickness and a.+-.15% variation in coverage across the wafer. Within a single wafer, the variation can commonly run as high as 900 .ANG., for a 3000 .ANG. thick film. Between wafers in a lot, there can be as much as a 1200 .ANG. variation.
A sidewall 31 made with film thicknesses subject to large variations will also show large variations in width. And if the width varies, then the lengths of the p-type first and n-type diffusion layers will likewise vary. This variation will appear as an uncontrolled variation in channel resistance for the affected transistors. The obvious result consequence is variations will be produced in transistor performance. As circuit geometries continue to get even finer with the advancing state-of-the-art, the channel length under the gates gets shorter, and the variations in series resistance gets more pronounced. As such, the above problem can limit using smaller device geometries, because device yields fall to unacceptable levels.
The present invention eliminates variations in the thickness of the sidewall, and therefore eliminates any variations in the lengths of the p-type and n-type diffusion layers. It also eliminates a source of impurities that can eventually poison a gate electrode and inject in the gate an artificial charge that affects the transistor's threshold voltage.